1. Field of the Invention
The present invention relates generally to integrated circuit devices, and more specifically to programmable logic devices which are configurable by a user.
2. Description of the Prior Art
Programmable logic devices are becoming increasingly popular in the electronics industry because of their flexibility. These devices allow a user to configure a standard part to perform a wide variety of standard logic functions. Since a single standard device can be configured many different functions, the total cost of using such a device in a system can be significantly less than the cost of custom designed parts; especially in cases where product volume is not extremely large.
Many programmable logic devices can be programmed only once. This may be done as a final metallization mask step at a silicon foundry. Another design is to provide a device which is programmable by the use of fusible links, with the programming being performed by the user using specialized programming equipment.
Other programmable logic device designs allow the devices to be reprogrammed by the user. These designs typically incorporate non-volatile memory such as EPROMs or EEPROMS to retain the programming, or configuration, information. If it is desired to reprogram the device, the configuration information stored in non-volatile memory on the device can be changed, which changes the functions performed by that device.
Reprogrammable logic devices can also be constructed using RAM, usually SRAM, to retain configuration information. Although such devices retain their configuration only so long as power is applied to the device, they are easily reprogrammed by the user. The use of RAM to perform logic functions has long been known. One approach to using RAM in a programmable logic device is to provide an array of identical logic blocks, also referred to as macrocells, which are interconnected by matrices of programmable switching elements.
Referring to FIG. 1, such a programmable logic device is referred to generally as 10. The device 10 contains an array of macrocells 12-15. Only 4 such macrocells are shown in FIG. 1, but a typical actual device would contain a much larger array.
The macrocells 12-15 are interconnected through programmable switching matrices 16-22. The programmable switching matrices 16-22 each contain a plurality of programmable switches for connecting pairs of signal lines passing therethrough. Their function is similar to the well known cross bar switch. By properly programming the switching matrices, signals can be routed between non-physically adjacent portions of the device 10. For example, an output signal from macrocell 14 can be used as an input to macrocell 13 by routing such signal through programmable switching matrices 21, 22, 20, and 17 in that order.
Inputs are supplied to the device through input buffers 24 connected to input pins 26. The signals from input buffers 24, preferably available in true and complemented versions, are connected to switching matrix 16. From this point, they can be routed to different parts of the device 10 as needed. Output buffers 28 are driven by signals routed through switching matrix 21, and drive output pins 30.
In many devices, the input/output pins are programmable as to their function. Thus, any given input/output pin can be programmed to be an input buffer 24 or an output buffer 28. Such technique is preferably used with the present invention, with input buffers 24 being those input/output buffers which have been programmed to be inputs, and output buffers 28 being those which have been programmed to be outputs.
The number of signal lines which connect various portions of the device 10 can be varied as desired. As shown in FIG. 1, each macrocell 12-15 has n inputs and m outputs. All macrocells are preferably identical for ease of design and layout. All programmable switching matrices 16-22 are also preferably identical, with the possible exception of matrices 16 and 21 used to communicate with the input buffers 24 and output buffers 28 respectively. k signal lines are routed between each programmable switching matrix. A typical, actual device 10 design might include, for example, a ten by ten array of macrocells, with programmable switching matrices between macrocells as indicated in FIG. 1. Each macrocell could have n=24 inputs and m=4 outputs, with k=32 signal lines between each programmable switching matrix.
In a device such as described in connection with FIG. 1, it would be desirable to have user RAM on the device. Unlike the RAM used to store configuration information, and thus defining logic functions, the user RAM would be available for use as a memory by the user.